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STK14C88-3
32K x 8 AutoStoreTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
FEATURES
* 35ns, 45ns and 55ns Access Times * "Hands-off" Automatic STORE with External 68F Capacitor on Power Down * STORE to nonvolatile elements Initiated by Hardware, Software or AutoStoreTM * RECALL to SRAM Initiated by Software or Power Restore * 10mA Typical ICC at 200ns Cycle Time * Unlimited READ, WRITE and RECALL Cycles * 1,000,000 STORE Cycles to nonvolatile elements (Commercial/Industrial) * 100-Year Data Retention in nonvolatile elements (Commercial/Industrial) * Single 3.3V + 0.3V Operation * Commercial and Industrial Temperatures * 32-Pin SOIC and DIP Packages
DESCRIPTION
The Simtek STK14C88-3 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent, nonvolatile data resides in nonvolatile elements. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) can take place automatically on power down. A 68F or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from "hot swapping". Transfers from the nonvolatile elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be software controlled by entering specific read sequences. A hardware STORE may be initiated with the HSB pin.
BLOCK DIAGRAM
VCCX Quantum Trap 512 x 512 VCAP POWER CONTROL
PIN CONFIGURATIONS
VCAP A14 A12 A7 A6 A5 A4 A3 NC A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A5 A6 A7 A8 A9 A11 A12 A13 A14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
STORE STATIC RAM ARRAY 512 x 512 RECALL STORE/ RECALL CONTROL HSB
INPUT BUFFERS
COLUMN I/O COLUMN DEC
SOFTWARE DETECT
A0 - A13
A0 A1 A2 A3 A4 A10
G E W
VCCX HSB W A13 A8 A9 A11 G NC A10 E DQ7 DQ6 DQ5 DQ4 DQ3
ROW DECODER
PIN NAMES
A0 - A14 Address Inputs DQ0 -DQ7 Data In/Out E Chip Enable W Write Enable G Output Enable HSB Hardware Store Busy (I/O) VCCX Power (+ 3.3V)
32 - DIP 32 - SOIC
VCAP Capacitor VSS Ground
48 - SSOP (not to scale)
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ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . -0.5V to 4.5V Voltage on Input Relative to VSS . . . . . . . . . .-0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .-0.5V to (VCC + 0.5V) Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL ICC
b
(VCC = 3.0V-3.6V)e
INDUSTRIAL MIN MAX 52 44 39 3 9 2 19 17 16 1 1 1 2.2 VSS - .5 2.4 VCC + .5 0.8 UNITS mA mA mA mA mA mA mA mA mA mA A A V V V 0.4 0.4 - 40 85 V V C tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels All Inputs Don't Care tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH tAVAV = 55ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA except HSB IOUT = 8mA except HSB IOUT = 3mA NOTES
PARAMETER Average VCC Current
COMMERCIAL MIN MAX 50 42 37 3 9 2 18 16 15 1 1 1 2.2 VSS - .5 2.4 0.4 0.4 0 70 VCC + .5 0.8
1
ICC ICC ICC ISB
c b
2 3 c
Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCAP Current during AutoStoreTM Cycle Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Logic "0" Voltage on HSB Output Operating Temperature
4
d 1
ISB
d 2
IILK IOLK VIH VIL VOH VOL VBL TA
Note b: Note c: Note d: Note e:
ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 2 4 E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. VCC reference levels throughout this datasheet refer to VCCX.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
3.3V
317 Ohms OUTPUT 351 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
CAPACITANCEf
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 5 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
Note f:
These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
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SRAM READ CYCLES #1 & #2
NO. 1 2 3 4 5 6 7 8 9 10 11 SYMBOLS #1, #2 tELQV tAVAVg tAVQVh tGLQV tAXQXh tELQX tEHQZi tGLQX tGHQZi tELICCHf tEHICCLf Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 35 0 13 0 45 5 5 13 0 15 0 55 35 35 15 5 5 15 0 20 STK14C88-3-35 MIN MAX 35 45 45 20 5 5 20 MIN
(VCC = 3.0V-3.6V)e
STK14C88-3-45 MAX 45 55 55 25 STK14C88-3-55 MIN MAX 55 UNITS ns ns ns ns ns ns ns ns ns ns ns
Note g: W and HSB must be high during SRAM READ cycles. Note h: I/O state asumes E and G < VIL and W > VIH; device is continuously selected. Note i: Measured 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT) 3 tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledg
2 tAVAV ADDRESS 6 1 tELQV 1 1 tEHICCL 7 tEHQZ
E
tELQX
G 8 4 tGLQV
9 tGHQZ
tGLQX DQ (DATA OUT)
DATA VALID
tELICCH
ACTIVE
10
ICC
STANDBY
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SRAM WRITE CYCLES #1 & #2
NO. 12 13 14 15 16 17 18 19 20 21 SYMBOLS #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ i, j tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW PARAMETER Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write 5 STK14C88-3-35 MIN 35 25 25 12 0 25 0 0 13 5 MAX MIN 45 30 30 15 0 30 0 0 15 5 MAX
(VCC = 3.0V-3.6V)e
STK14C88-3-45 STK14C88-3-55 MIN 55 40 40 25 0 40 0 0 20 MAX UNITS ns ns ns ns ns ns ns ns ns ns
Note j: If W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ DATA OUT
PREVIOUS DATA HIGH IMPEDANCE DATA VALID
19 tWHAX
tAVWL W
18
16 tWHDX
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledk, l
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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HARDWARE MODE SELECTION
E H L L X W X H L X HSB H H H L A13 - A0 (hex) X X X X MODE Not Selected Read SRAM Write SRAM Nonvolatile STORE I/O Output High Z Output Data Input Data Output High Z POWER Standby Active Active lCC
2
NOTES
t
m
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE STORE CYCLE
NO. 22 23 24 25 26 SYMBOLS Standard tSTORE tDELAY tRECOVER tHLHX tHLBL Alternate tHLHZ tHLQZ tHHQX STORE Cycle Duration Time Allowed to Complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy PARAMETER
(VCC = 3.0V-3.6V)e
STK14C88-3 MIN MAX 10 1 700 15 300 UNITS ms s ns ns ns NOTES i, n i, n n, o
Note n: E and G low and W high for output behavior. Note o: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25 tHLHX HSB (IN) 24 tRECOVER 22 tSTORE
HSB (OUT)
26 tHLBL
HIGH IMPEDANCE HIGH IMPEDANCE
23 tDELAY DQ (DATA OUT)
DATA VALID DATA VALID
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AutoStoreTM/POWER-UP RECALL
NO. 27 28 29 30 31 32 SYMBOLS Standard tRESTORE tSTORE tVSBL tDELAY VSWITCH VRESET tBLQZ tHLHZ Alternate PARAMETER Power-up RECALL Duration STORE Cycle Duration Low Voltage Trigger (VSWITCH) to HSB Low Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level 1 2.7 2.95 2.4
(VCC = 3.0V-3.6V)e
STK14C88-3 MIN MAX 550 10 300 UNITS s ms ns s V V NOTES p n, q l n
Note p: tRESTORE starts from the time VCC rises above VSWITCH. Note q: HSB is asserted low for 1s when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no STORE will take place.
AutoStoreTM/POWER-UP RECALL
VCC 31 VSWITCH 32 VRESET
AutoStoreTM
POWER-UP RECALL 27 tRESTORE HSB
29 tVSBL
28 tSTORE
30 tDELAY W
DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT NO STORE (NO SRAM WRITES) NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStoreTM NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStoreTM RECALL WHEN VCC RETURNS ABOVE VSWITCH
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SOFTWARE STORE/RECALL MODE SELECTION
E W A13 - A0 (hex) 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63 MODE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z POWER NOTES
L
H
Active
r, s, t
lCC
2
L
H
Active
r, s, t
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv
NO. 33 34 35 36 37 SYMBOLS Standard tAVAV tAVEL tELEH tELAX tRECALL Alternate tRC tAS tCW PARAMETER STORE/RECALL Initiation Cycle Time Address Set-up Time Clock Pulse Width Address Hold Time RECALL Duration STK14C88-3-25 MIN 35 0 25 20 20 MAX STK14C88-3-35 MIN 45 0 30 20 20 MAX
(VCC = 3.0V-3.6V)e
STK14C88-3-45 MIN 55 0 45 20 20 MAX UNITS ns ns ns ns s NOTES n u u u
Note r: Note s: Note t: Note u: Note v:
The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes. I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. The software sequence is clocked with E controlled READs. The six consecutive addresses must be in the order listed in the Hardware Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDv
tAVAV ADDRESS
34 ADDRESS #1 33
tAVAV
ADDRESS #6
33
tAVEL E
tELEH
35
tELAX tSTORE DQ (DATA
DATA VALID DATA VALID 28 37 / tRECALL
36
HIGH IMPEDANCE
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DEVICE OPERATION
The STK14C88-3 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to nonvolatile elements (the STORE operation) or from nonvolatile elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled.
POWER-UP RECALL
During power up, or after any low-power condition (VCAP < VRESET), an internal RECALL request will be latched. When VCAP once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK14C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC.
NOISE CONSIDERATIONS
The STK14C88-3 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCAP and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SOFTWARE NONVOLATILE STORE
The STK14C88-3 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
SRAM READ
The STK14C88-3 performs a READ cycle whenever E and G are low and W and HSB are high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
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SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed:
68F 6v, 20% 10k 10k
1 32 31 30
1. 2. 3. 4. 5. 6.
Read address Read address Read address Read address Read address Read address
0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex)
Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
+
0.1F Bypass
16
17
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
Figure 2: AutoStoreTM Mode *If HSB is not used, it should be left unconnected.
AutoStoreTM OPERATION
During normal AutoStoreTM operation, the STK14C88-3 will draw current from VCCX to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX and initiate a STORE operation. Figure 2 shows the proper connection of capacitors for automatic store operation. A charge storage capacitor having a capacity of between 68F and 220F ( 20%) rated at 4.7V should be provided. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low, will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether a WRITE operation has taken place. An optional pull-up resistor is shown connected to HSB. This can be used to signal the system that the AutoStoreTM cycle is in progress.
If the power supply drops faster than 20 s/volt before VCCX reaches VSWITCH, then a 1 ohm resistor should be inserted between VCCX and the system supply to avoid a momentary excess of current between Vccx and Vcap.
HSB OPERATION
The STK14C88-3 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14C88-3 will conditionally initiate a STORE operation after tDELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14C88-3 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple STK14C88-3s while using a single larger capacitor.
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To operate in this mode the HSB pin should be connected together to the HSB pins from the other STK14C88-3s. An external pull-up resistor to + 3.3V is required since HSB acts as an open drain pull down. The VCAP pins from the other STK14C88-3 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK14C88-3s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK14C88-3s that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK14C88-3 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14C88-3 will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected.
Average Active Current (mA) 50
Average Active Current (mA)
40
30
20 TTL 10 CMOS 0 50 100 150 Cycle Time (ns) 200
Figure 3: Icc (max) Reads
50
HARDWARE PROTECT
The STK14C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM WRITEs will be inhibited.
40
30 TTL CMOS 10
20
LOW AVERAGE ACTIVE POWER
The STK14C88-3 draws significantly less current when it is cycled at times longer than 55ns. Figure 3 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Figure 4 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88-3 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading.
0 50 100 150 Cycle Time (ns) 200
Figure 4: Icc (max) Writes
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STK14C88-3 ORDERING INFORMATION
STK14C88-3 N F 45 I Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
35 = 35ns 45 = 45ns 55 = 55ns
Lead Finish
Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin)
Package
N = Plastic 32-pin 300 mil SOIC W = Plastic 32-pin 600 mil DIP R = Plastic 48-pin 300 mil SSOP
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Document Revision History
Revision 0.0 0.1 0.2 0.3
Date January 2003 February 2003 September 2003 November 2003
Summary Added 35 nsec device; added HSB operation; current limiting resistor added to Vccx for extreme power-off slew rate Added 48 SSOP package Added lead-free lead finish Modified pin assignments on 48 SSOP package
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